1. Field of the Invention
The present invention relates to a display device which performs display control on pixels by using a thin-film transistor (TFT), and a manufacturing method of the display device.
2. Description of the Related Art
Heretofore, studies have been made to improve electric characteristics or the like of a thin-film transistor formed with amorphous silicon (a-Si) so as to achieve higher performance thereof. Here, in order to attain desired electric characteristics in a thin-film transistor formed with amorphous silicon, studies have also been made in a direction that the mobility of electrons are increased by increasing a grain size of the silicon, without changing to the extent possible the structure of the thin-film transistor formed with amorphous silicon so that a designed manufacturing process can still be employed.
JP 05-55570 A discloses an example of the above-mentioned technology, and FIG. 6 is a diagram illustrating a thin-film transistor with a bottom-gate structure similar to that disclosed in JP 05-55570 A. According to JP 05-55570 A, as illustrated in the drawing, a polycrystalline silicon (p-Si) layer is laminated below an amorphous silicon layer, due to the manufacturing of the display device.
In the case of the thin-film transistor illustrated in FIG. 6, an on-state current flows through the polycrystalline silicon layer SP of high electron mobility. On the other hand, there arises a problem when an off-state current flows therethrough. When a negative voltage is applied to a gate electrode GT, positive holes are induced to the polycrystalline silicon layer SP and a current due to the positive holes directly flows into a drain electrode DT and a source electrode ST because there is provided no potential barrier between the polycrystalline silicon layer SP and each of the drain electrode DT and the source electrode ST.
In order to solve the problem, the inventors of the present invention have first studied a structure illustrated in FIG. 7. As illustrated in FIG. 7, a polycrystalline silicon layer SP and an amorphous silicon layer SA are each covered with an impurity silicon layer (Doped-Si) DS formed of amorphous silicon doped with an impurity, to thereby prevent the passage of positive holes, with the result that an off-state current is suppressed. However, the polycrystalline silicon layer SP is connected to the drain electrode DT and to the source electrode ST through the impurity silicon layer DS with a small contact area, which increases contact resistance, leading to an insufficient on-state current.
With this being the situation, the inventors of the present invention have further studied a structure illustrated in FIG. 8. In order to increase the on-state current in the structure of FIG. 7, an area across which the semiconductor film S is connected to the drain electrode DT and to the source electrode ST is increased as illustrated in FIG. 8, to thereby reduce the contact resistance. To attain this structure, an insulating film ES is first formed in place of the amorphous silicon layer SA, so that the semiconductor film S contacts with the impurity silicon layer DS at portions not covered with the insulating film ES.
However, with the structure illustrated in FIG. 8, as can be understood from the graph of FIG. 9A which illustrates the volt-ampere characteristics between the gate voltage and the drain current, a sufficient on-state current is secured at a drain voltage of 1V while suppressing the off-state current, whereas at a drain voltage of 10V, the off-state current cannot be suppressed and allows a leak current to flow. Accordingly, a drain voltage to be applied to the thin-film transistor needs to be limited to, for example, 5V or less, and there still remains a problem of how to suppress the off-state current in a case of increasing the drain voltage to a higher voltage.